1. Field of the Invention
The present invention relates generally to testing semiconductor memory devices, and more particularly, to a semiconductor memory device having on-chip test circuit for testing one transistor and one capacitor type memories.
2. Description of the Background Art
Due to the development of the manufacturing technique of semiconductor integrated circuits and to the user's request on cost reduction, the degree of integration of a DRAM is increased quadruple in about three years, and today DRAMs having a capacity of 4M bits have come into use. In such a DRAM, for example, a data read/write test is carried out wherein when data "0" are written in all the memory cells, the data "0" are read out from all the memory cells, and the same operation is performed with respect to the data "1" in the cycle time of 10 .mu.sec. (maximum pulse width of a RAS (row address strobe) signal), the test time T1 for testing will be represented by the following equation (1). EQU T1=4 (writing of "0"&gt;reading of "0"&gt;writing of "1"&gt;reading of "1").times.4.times.10.sup.6 (memory capacity).times.10 .mu.sec (cycle time)=160 sec. (1)
In case of a conventional dynamic RAM, the data read/write test should be performed at least under four different conditions, namely, at the maximum value 5.5 V and the minimum value 4.5 V of the operational range of a power supply voltage, and at the higher temperature 70.degree. C. and the lower temperature 0.degree. C. of the operational temperature range.
In this case, the test time T2 for testing will be represented by the equation (2). EQU T2=160 sec..times.4=640 sec. (2)
The above described value is extremely large as a test time for an integrated circuit, which causes reduction of the productivity and the increase in cost.
In addition, the above described test is not sufficient for detecting defects in some cases. Other test should be performed by combining timings of input signals, addressing order of address signals, patterns of data to be written in the memory cells, and so on. Such combination test requires a long period of time.
In testing a memory cell, it is to important to read the voltage from the memory cell. Assuming that when a voltage of 100 mV or more is read as data from the memory cell, the memory cell operates normally, if a voltage of 200 mV is read from a memory cell, it is determined that the memory cell is good because it has an operation margin of 100 mV for the voltage of 100 mV. However, in case a voltage of 110 mV is read from a memory cell, an operation margin is as small as 10 mV for the voltage of 100 mV. A voltage read from a memory cell varies depending on the conditions, so that there are cases in which a voltage of only 90 mV is read from a memory cell outputting a voltage of 110 mV.
More specifically, since the bit lines are adjacent to each other, as a memory capacitance is increased, there appears a capacitance between the bit lines, whereby a coupling capacitance is changed depending on whether the adjacent bit lines are of "1" or "0", so that a voltage read from the memory cell becomes 90 mV or 110 mV. Therefore, if a memory cell which read voltage is 110 mV is good, the memory cell is considered to be defective depending on the conditions of the usage.
A power supply voltage fluctuation test (referred to as V bump test hereinafter) has been employed, by which operation margins of memory cells can be tested in a short period of time, considering that almost all the memory cells malfunction in the combination test have small operation margins. The V bump test is a testing of a memory cell based on the fact that fluctuation of a power supply voltage, a V bump, reduces a reading margin and increases an access time period. The V bump is divided into a Vcc bump which is a fluctuation of a power supply voltage and a V.sub.BB bump which is a fluctuation of a substrate voltage. The Vcc bump has two types based on a direction of the bump, one of which is referred to as a positive Vcc bump in which after data is written in a memory cell with a low power supply voltage Vcc, if the data is read from the memory cell with a high power supply voltage Vcc, a reading margin of the memory cell is reduced and even an error is caused. The other is a mode referred to as a negative Vcc bump which is further divided into modes wherein after data is written with a high power supply voltage Vcc, if the data is read with a low power supply voltage Vcc, an access time is delayed in one mode and an erroneous operation is caused in the other. The V.sub.BB bump is a problem peculiar to a dynamic RAM containing a substrate voltage generating circuit, and which fluctuation reduces a reading margin of a memory cell. However, as the memory capacity becomes larger and larger, the effect of the V bump test has been lost. The reason for this will be described in the following with reference to FIGS. 10 to 14.
FIG. 11 is a block diagram showing a schematic structure of an entire reading portion of a DRAM to which the present invention is applied.
In FIG. 11, the DRAM comprises a memory cell array MA, an address buffer AB, an X decoder ADX, a Y decoder ADY, a sense amplifier and I/O SI and an output buffer OB. The memory cell array MA comprises a plurality of memory cells arranged in rows and columns for storing information, and the address buffer AB receives external address signals applied from an exterior to generate internal address signals. The X decoder ADX decodes the internal address signals applied from the address buffer AB to select a corresponding row in the memory cell array. The Y decoder ADY decodes internal column address signals applied from the address buffer AB to select a corresponding column in the memory cell array MA.
The sense amplifier and I/O SI detects and amplifies information stored in the selected memory cell in the memory cell array MA, and outputs the information as read data to the output buffer OB in response to a signal from the Y decoder ADY. The output buffer OB receives the read data to output the output data Dout to the exterior. A control signal generating system CG is provided as a peripheral circuit for generating control signals for controlling timings of various operations of the DRAM.
FIG. 12 is a diagram showing a schematic structure of the memory cell array shown in FIG. 11.
In FIG. 12, the memory cell (array MA) comprises a plurality of word lines WL1, WL2, . . . , WLn and a plurality of bit lines BL0, BL0, BL1, BL1, . . . , BLm, BLm. Each of the word lines WL1, . . . , WLn is connected to one row of the memory cells. The bit lines are formed as a folded bit line type, in which two bit lines constitute a bit line pair. Namely, the bit lines BL0 and BL0 constitute one bit line pair, the bit lines BL1 and BL1 constitute one bit line pair and the bit lines BLm and BLm constitute one bit line pair, in the same manner.
Memory cells 1 are connected to intersections of the respective bit lines BL0, BL0, . . . , BLm, BLm and every other word lines. Namely, a memory cell is connected to an intersection of one word line and either of the paired bit lines. A precharging/equalizing circuit 150 for equalizing potentials of each bit line pair and precharging the same to a predetermined potential V.sub.B is provided at each bit line pair. A sense amplifier 50 is provided for each bit line pair, which is activated in response to signals .phi..sub.A and .phi..sub.B transmitted on signal lines 20 and 30, for detecting and differentially amplifying the potential difference between the bit line pair. Each bit line is selectively connected to data input/output buses I/O, I/O in response to an address decode signal from the Y decoder ADY. Namely, the bit lines BL0 and BL0 are connected to the data input/output buses I/O and I/O through transfer gates T0 and T0', respectively.
In the same manner, the bit lines BL1 and BL1 are connected to the data input/output buses I/O and I/O through transfer gates T1 and and T1', respectively, and the bit lines BLm and BLm are connected to the data input/output buses I/O and I/O through transfer gates Tm and Tm', respectively. The address decode signals from the Y decoder ADY are transmitted to gates of the respective transfer gates T0, T0', . . . , Tm, Tm'. Thus, a pair of bit lines is connected to the data input/output buses I/O and I/O.
FIG. 13 is a diagram showing a detailed structure of one of the bit line pairs shown in FIG. 12. In FIG. 13, only one word line and one bit line pair are shown for the purpose of simplicity.
In FIG. 13, a precharging/equalizing circuit 150 is provided for precharging a pair of bit lines 2 and 7 to a predetermined potential V.sub.B when the memory is on standby and for equalizing potentials of the bit lines 2 and 7 to predetermined potentials. The precharging/equalizing circuit 150 comprises n channel MOS transistors 10 and 11 responsive to a precharging signal .phi..sub.P generated by control generating system CG in FIG. 11 for electrically connecting the bit lines 2 and 7 by transmitting predetermined perchance potentials to the bit lines 2 and 7, respectively, and for equalizing the potential of the bit lines 2 and 7 at the precharge potential. Both of the n channel MOS transistors 10 and 11 are rendered conductive in response to the precharging signal .phi..sub.P applied through a signal line 12 and apply the precharge potential V.sub.B transmitted on a signal line 9 to the bit lines 2 and 7.
The memory cell 1 comprises a transfer gate 5 formed of an n channel insulated gate field effect transistor, and a capacitance 6. The transfer gate 5 has a gate connected to a word line 3 and a source connected to the bit line 2. The capacitance 6 is connected to a drain of the transfer gate 5 through a node 4, where the data of the memory cell 1 is stored. The node 4 forms a so-called storage node.
When the word line 3 is selected, a word line driving signal Rn is transmitted to the transfer gate 5 to render the same conductive, whereby the information stored in the memory cell 1 is transferred onto the bit line 2. Memory cells 1 (only one cell is shown) are connected to the bit line 7, while no memory cell is connected to an intersection of the word line 3 and the bit line 7. Therefore, when the memory cell 1 shown in FIG. 12 is selected, the bit line 7 applies a reference potential for the bit line 2. The bit lines 2 and 7 form parasitic capacitances 13 and 14, respectively.
The area of the memory cell has been made smaller and the capacity of the memory cell has also been made smaller as a degree of integration (memory capacitance) has been increased. However, in order to prevent malfunctions (soft errors) of a DRAM due to .alpha. rays emitted from an package of the DRAM, a memory cell capacitance value of at least about 50 fF is generally required. Therefore, it is a general practice to compensate for the reduction of a memory cell capacitance due to the reduction of the memory cell area by reducing the film thickness of the dielectric. However, when the film thickness of the dielectric is reduced, the electric field applied into the insulating film becomes strong, causing possible breakdown of the insulating film and lowering the reliability of the DRAM. This problem has become acute especially by 1M bit DRAMs used at present. In order to cope with the problem, it has become a common practice to supply a voltage of half the power supply voltage divided by the resistances 17 and 18 to an electrode on the power supply side (referred to as a cell plate electrode hereinafter) of the memory cell capacitance, as shown in FIG. 13. Resistances 17 and 18 forming a constant voltage generating circuit are connected in series between a power supply 16 and a ground, and a constant voltage defined by resistance division is generated at a node of the resistances 17 and 18. The resistance values of the resistances 17 and 18 are selected such that a level of the voltage is half the general power supply voltage. An output voltage of the constant voltage generating circuit is applied to one electrode of the capacitance 6 through a signal line 8. The capacitance 6 is formed of parallel plate electrodes with the dielectric being a thin insulating film such as a single layer silicon oxide or a multi-layered film of silicon oxide and silicon nitride, and a size thereof is dependent on an area of the memory cell. This approach is disclosed in Japanese Patent Publication No. 60-50065 (U.S. Ser. No. 722,841). According to the Japanese Patent Publication, the electric field is determined by a voltage difference between the storage node 4 and the cell plate electrode, and since the voltage of the cell plate becomes an intermediate value between the data "1" and "0", the electric field is reduced by half.
However, the application of the voltage half as large as the power supply voltage to the cell plate electrode makes it difficult to detect memory cells having small operation margins in the V bump test. The reasons will be described in the following.
In the DRAMs having a capacity of less than 1M bits, an insulating film constituting a dielectric of a memory cell capacitance is relatively thick (about 150 .ANG.-200 .ANG. in a DRAM of 256 k bits), and therefore there has been little need to set the voltage of the cell plate electrode at 1/2 Vcc. As a result, a voltage of Vcc or 0 level is supplied from a power supply line or from a ground line which has small impedance and therefore little noise. The constant voltage generating circuit shown in FIG. 13 has relatively high impedance and is liable to generate noise during the operation of the DRAM which reduces operation margin thereof, and therefore it has not been used.
The effects of the V bump test in case where levels of the cell plate electrode are the power supply voltage Vcc, ground (fixed level) and Vcc/2, respectively, will be compared in the following.
(1) The level of the cell plate electrode is power supply voltage Vcc: (in case the signal line 8 shown in FIG. 13 is connected to Vcc as shown by the dotted line) PA1 (2) The level is fixed (in case the cell plate voltage is fixed with respect to the Vcc fluctuation, namely, the signal line 8 is grounded as shown by the dotted line): PA1 (3) The level is 1/2 Vcc (in case the signal line 8 is connected between the resistances 17 and 18 in FIG. 13):
Voltage waveforms of respective nodes concerned in the V bump test are shown in FIGS. 14 and 15. The V bump test is carried out by writing data in the memory cell 1 with a certain supply voltage Vcc, raising the power supply voltage Vcc by a certain level as shown in FIG. 14 (a), and thereafter by reading the data from the memory cell 1. In FIG. 14, the data is written with the power supply voltage Vcc and the data is read with the voltage Vcc+.DELTA.V. The precharge potential V.sub.B is set at a value equal to half the power supply voltage Vcc, which is as shown in FIG. 14(b). The storage node 4 is at 0 V in writing since it is assumed that the data "0" is written in the storage node 4. Now assuming that because of the connection of the storage node 4 to the signal line 8 through the capacitance, a voltage of the storage node 4 rises by the amount of fluctuation when the power supply voltage of the signal line 8 fluctuates, as shown in FIG. 14(c). At this time, the levels of the bit lines 2 and 7 change with the precharge potential V.sub.B to be approximately the same level as the precharge potential V.sub.B.
An operation of reading data from the memory cell 1 will be described in the following with reference to FIG. 15. As shown in FIG. 14(a), when the precharge signal .phi..sub.P goes low level at the time t.sub.0, the signal line 9 and the bit lines 2 and 7 are non-equalized from each other. When the word line driving signal Rn rises at the time t.sub.1 as shown in FIG. 15(b), the MOS transistor 5 is rendered conductive, a current flows from the bit line having a higher potential to the storage node 4, whereby the potential on the bit line 2 drops as shown in FIG. 15(c) and the potential on the storage node 4 rises as shown in FIG. 15(d). At the time t.sub.2 the potentials almost do not change, so that the reading levels on the bit lines 2 and 7 are set. The levels on the bit lines 2 and 7 on this occasion will be represented by the following equations.
Considering that a principle of the conservation of electric charges is established between the bit line 2 and the storage node 4 before and after the conduction of the MOS transistor 5, the following equation will be obtained: EQU 1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +.DELTA.V.multidot.C.sub.6 =(C.sub.13 +C.sub.6).multidot.V.sub.BO ( 3) EQU V.sub.BO =1/(C.sub.13 +C.sub.6).multidot.[1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +.DELTA.V.multidot.C.sub.6 ] (4)
wherein V.sub.BO denotes a bit line voltage on a reading side when "0" is read after the V bump test.
A voltage difference VSO with the bit line 7 will be represented by the following equation: EQU V.sub.SO =1/(C.sub.13 +C.sub.6).multidot.[1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +V.multidot.C.sub.6 ]-1/2.multidot.(Vcc+.DELTA.V) (5) EQU =-1/2.multidot.C.sub.6 /(C.sub.13 +C.sub.6).multidot.(V.sub.cc +.DELTA.V)(6)
wherein V.sub.SO denotes a voltage obtained by subtracting a voltage on the other side from V.sub.BO.
Accordingly, the voltage difference becomes smaller by the amount of .DELTA.V, producing the V bump effect.
When the data "0" is written in the memory cell 1, the following equations will be obtained. EQU 1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 =(C.sub.13 +C.sub.6).multidot.V.sub.BO ( 7) EQU V.sub.BO =1/(C.sub.13 +C.sub.6 [1/2(Vcc+.DELTA.V).multidot.C.sub.13 ](8) EQU V.sub.SO =1/(C.sub.13 +C.sub.6)[1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 ]-1/2.multidot.(Vcc+.DELTA.V) (9) EQU V.sub.SO =-1/2.multidot.C.sub.6 /(C.sub.13 +C.sub.6).multidot.(Vcc+.DELTA.V)(10)
For the data "0", the V bump produces a reverse effect, to enlarge the voltage difference. When the data "1" is written in the memory cell 1, the following equations will be obtained. EQU 1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +(Vcc+.DELTA.V) C.sub.6 =(C.sub.13 +C.sub.6)V.sub.B1 ( 11) EQU V.sub.B1 =1/(c.sub.13 +C.sub.6).multidot.[1/2(Vcc+.DELTA.V).multidot.C.sub.13 +(Vcc+.DELTA.V).multidot.C.sub.6 ] (12) EQU V.sub.S1 =1/2.multidot.C.sub.6 /(C.sub.13 +C.sub.6).multidot.(Vcc-.DELTA.V)(13)
For the data "1", the voltage difference becomes smaller, and therefore, there occurs V bump effect.
In this case, a voltage level of the cell plate electrode changes only by 1/2.multidot..DELTA.V, so that the level on the storage node 4 of the memory cell 1 will change also by 1/2.multidot..DELTA.V. Calculating in the same manner as the above description, the following equations will be obtained, ##EQU1## EQU V.sub.BO =1/(C.sub.13 +C.sub.6 [1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +1/2.multidot..DELTA.V.multidot.C.sub.6 ] (15) ##EQU2## wherein there is no term .DELTA.V included, and therefore there occurs no V bump effect.
When the data "1" is written in the memory cell, the following equations will be obtained, EQU 1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +(Vcc+1/2.multidot..DELTA.V).multidot.C.sub.6 =(C.sub.13 +C.sub.6).multidot.V.sub.B1 ( 18) EQU V.sub.B1 =1/(C.sub.13 +C.sub.6)[1/2.multidot.(Vcc+.DELTA.V).multidot.C.sub.13 +(Vcc+1/2.multidot..DELTA.V).multidot.C.sub.6 ( 19) ##EQU3## wherein there is no term .DELTA.V included, and therefore, there occurs no V bump effect.
FIG. 16 shows the above described relations.
From the above described results, it is found that a reading margin of a memory cell will be different in case of the cell plate voltage being Vcc or fixed, and in case of 1/2.multidot.Vcc. More specifically, when the cell plate voltage is Vcc or it is fixed, a voltage difference between a pair of bit lines, that is, a voltage difference between the inputs of the sense amplifier changes depending on .DELTA.V, so that a reading margin of the memory cell can be tested by .DELTA.V. However, when it is 1/2.multidot.Vcc, the input voltage difference of the sense amplifiers cannot be changed depending on .DELTA.V, and therefore the reading margin of the memory cell cannot be tested by using .DELTA.V.